This application claims priority from Canadian Patent application 2,342,516 filed Mar. 30, 2001 and Canadian Patent application 2,342,472 filed Mar. 30, 2001.
The present invention relates to semiconductor memories. In particular the invention relates to memory row decoders.
DRAM memory cells consist of a single transistor and storage capacitor, where the storage capacitor can be formed as a planar, trench or stacked capacitor. DRAM memories are generally accessed by supplying a row address and a column address to access memory cells within the memory array. More specifically, the row address activates a selected wordline and the column address enables data to be transferred between selected complementary bitline pairs and a databus. The following description briefly highlights how memory cells are accessed in a memory array.
FIG. 1 shows a general block diagram of a DRAM of the prior art. Only the core circuits peripheral to the memory array are shown to simplify the schematic, however, those of skill in the art will understand that other DRAM circuits are required for its proper operation. DRAM 10 of FIG. 1 includes a master row decoder 12, row decoders 14, bitline access circuit blocks 16 and memory array 18. Bitline access circuit blocks 16 include bitline sense amplifiers, precharge circuits and column access devices. Memory array 18 consists of bitlines and wordlines, with memory cells located at the crossing points of the wordlines and bitlines. A detailed schematic of a memory array that can be used for memory array 18 is shown in FIG. 2. In a read access operation for example, master row decoder 12 receives a portion of row address signals for generating predecoded row address signals used by row decoders 14. Predecoding row address signals is typically done for selecting subsets of row decoders. In addition to receiving the predecoded row address signals, row decoders 14 receive another portion of row address signals for driving a selected wordline of memory array 18. The bitline sense amplifiers of blocks 16 amplifies the voltage level of the bitlines after memory cell transistors are activated via the selected wordline. Column access devices of blocks 16 receive column address signals for coupling selected complementary bitlines to common databus DB. The number of column access devices activated by any one column address is determined by the configuration of the DRAM. For example, if the DRAM is configured to be a xc3x974 data width device, then memory array 18 provides four bits of data onto four complementary pairs of databuses in parallel. Those of skill in the art should understand that databus DB represents a predetermined number of pairs of complementary databus lines, and that the data width configuration of DRAM 10 is fixed.
FIG. 2 illustrates a well known arrangement of memory cells, wordlines and bitlines of memory array 42 in FIG. 1. In this particular example four bitlines, ten wordlines labelled as WL to WL+9, and a corresponding number of memory cells are shown arranged in a folded bitline configuration. Each sense amplifier and column access block 31 is connected to a pair of complementary bitlines 30/32 labelled as BLi, BLi*, and 44/46 labelled as BLi+1, BLi+1*. Each wordline is driven by row decoders 14 of FIG. 1, and each individual sense amplifier and column access block 31 is part of a block 16 in FIG. 1. It should be apparent to those of skill in the art that each block 31 also includes bitline precharge devices. Complementary bitlines 30/32 and 44/46 extend in parallel from one side of its respective sense amplifier and column access block 36. Planar capacitor cells 36 are connected to each of the bitlines 30 and 32 via a respective bitline contact 42. Bitlines 30 and 32 are typically formed of aluminum above the cells 36 and polysilicon wordlines 34. Each cell 36 includes a cell plate diffusion, or active area 38 and an access transistor active area 40. Polysilicon wordlines 34 run in a direction perpendicular to the bitline direction, and cross over access transistor diffusion areas 40 of any cell 36 in their path. Each cell 36 stores a single bit of data, represented as a voltage level stored on the storage capacitor. Single ended sensing is used to read out this data, in which a wordline such as WL is activated to couple a storage capacitor of a cell 36 to its corresponding bitline 32. Since all complementary bitlines 30/32 and 40/46 are precharged to a mid-point voltage level, bitline 30 is used as a reference voltage level for the bitline sense amplifier of block 31. The precharged voltage level of bitline 32 will change by a few hundred milli-volts when a cell 36 is coupled to it. Those of skill in the art will understand that the memory cells can also be trench or stacked capacitor DRAM cells.
The previously described read access operation is referred to as a random access operation if different wordlines are activated in each access cycle. However, an extension of the read access operation is a page mode read operation for successively reading and writing data to the memory at a faster rate than repeated random accesses. Most systems desire fast data access speeds to achieve faster overall system performance since memory access speeds tend to bottleneck system performance.
DRAM 10 is capable of operating in page mode, where data is successively accessed from the same activated wordline or row of memory array 18. This means that a page of data can be accessed, where each page includes a finite number of words. For example, if memory array 18 provides an 8-bit wide word of data for each column address, and each column address can select one of four different words, then four words can be successively accessed in page mode operation. The advantage of page mode access is higher throughput of data than if the page was randomly accessed. Page mode access is well known in the art, and therefore does not require further discussion. Hence, page mode access is useful when a system needs to store and retrieve successive words of data quickly on the same page.
In the page mode discussion above, DRAM 10 was described as having an 8-bit data width. DRAM 10 can also be configured for 1, 4, 8 and 16 bit wide configurations for example. This is because different configurations are preferable for specific applications. These different configurations are permanently set by the manufacturer through bond options or fuses.
Some of the disadvantages with conventional DRAM memories are now discussed.
DRAM is susceptible to soft errors caused by alpha particle bombardment for example, which can unpredictably change the voltage level of the bitlines. Since the bitline sense amplifiers have low sensing margins to detect the few hundred milli-volt difference between the pair of complementary bitlines, alpha particle bombardment can cause misreads from the memory array. The effects of alpha particle bombardment could be reduced by increasing the sensing margin of the bitline sense amplifiers. DRAM also requires constant refreshing of its data in order to maintain its stored data due to inherent charge leakage of its storage capacitor. DRAM devices that require more frequent refreshing will consume more refresh power, which is exacerbated when the DRAM operates in abnormal voltage or temperature conditions. High power consumption due to refresh operations is undesirable, especially during a power down or sleep mode when the DRAM is not in use. Therefore, such DRAM""s are not suitable for portable applications where power is limited.
The page length of the DRAM is set by the manufacturer and thus does not necessarily meet the requirements of a specific application. If the application requires access to a page of data greater than that provided by the DRAM, then a second page, or wordline, must be accessed. Activation of a second wordline introduces additional latency that slows the overall throughput of data. Although DRAM manufacturers can provide devices having larger pages to accommodate these specific applications, these devices would neither be cost effective or practical for such limited applications. Furthermore, large page mode DRAM devices would consume more power during random accesses than DRAM devices having shorter pages, since more bitlines and sense amplifiers are simultaneously activated in the large page mode DRAM device. Therefore a DRAM having slow throughput and higher power consumption is less attractive for use in applications where high speed is required, or in portable applications where power is limited.
Because of the different data width configurations required by different applications, a DRAM manufacturer attempts to provide as many of the configurations as possible by manufacturing a single generic DRAM device. This generic DRAM is programmable by fuses or bond options to permanently set the configuration of the DRAM. However, the additional overhead required for setting the generic DRAM device into a specific configuration can be costly. The indirect cost can also be high in a situation where the supply of one configuration does not meet the demand, and there is an excess supply of a different configuration. The manufacturer must either increase production for producing the demanded configuration, or risk losing market share to competitors. Even if the manufacturer is able to manufacture more of the demanded configuration, there remains an excess supply of the different configuration that cannot be sold.
Embedding DRAM for system on chip applications is becoming a predominant method of integrating DRAM memory and microcontroller logic for increasing overall device performance of the device that uses it, and reducing the size of the device. Unfortunately, the embedded DRAM is still susceptible to alpha particle bombardment as in commodity DRAMs. Although embedded DRAM utilizes data widths wider than most commodity DRAMs, system on chip designs are still limited to the preselected data width set by the manufacturer. Embedded DRAM also has fixed page sizes that may not meet the specific system requirements. Hence overall system design flexibility is limited.
Therefore, there is a need for a DRAM that is tolerant to alpha particle bombardment and consumes less power while providing higher sensing margins. There is also a need for a DRAM that allows system designers to adjust the page size as required, and to change the data width configuration as required for system design flexibility.
It is an object of the present invention to obviate or mitigate at least one disadvantage of the prior art. In particular, it is an object of the present invention to provide a row addressing circuit that can dynamically switch a DRAM between various access modes to increase data access throughput speed and to reduce refresh power consumption.
In a first aspect, the present invention provides a master row decoder circuit for enabling bitline access circuit blocks and row decoder blocks. The master row decoder circuit includes column enabling logic and row enabling logic. The column enabling logic enables between one half of the bitline access circuit blocks and all of the bitline access circuit blocks in response to a first row address signal and a page mode signal. The row enabling logic enables activation of at least one wordline in each row decoder block in response to a second row address signal and a differential access mode signal, where the row enabling logic enables the row decoder block corresponding to the enabled bitline access circuit block.
In a second aspect, the present invention provides a method for operating DRAM memory having row decoder blocks and bitline access circuit blocks. The method includes providing a page mode signal for switching the DRAM memory between a long page access mode and a short page access mode, providing a differential access mode signal for switching the DRAM memory between single cell per bit and dual cell per bit modes, decoding the page mode signal and a first row address signal for generating column control signals, where the column control signals enabling between one half and all of the bitline access circuit blocks, decoding the differential access mode signal and a second row address signal for generating row decoder control signals, and decoding the column control signals and the row decoder control signals for generating predecoded row address signals, where the predecoded row address signals enable activation of at least one wordline in each row decoder block.
In an alternate embodiments of the present aspect, all the row decoder blocks and all the bitline access circuit blocks are enabled when the DRAM memory operates in the long page access mode, and a plurality of row address signals are provided to all the row decoder blocks.
In another embodiment of the present aspect, the row address signal is column decoded with column address signals when the DRAM memory operates in the long page access mode.
In yet another embodiment of the present aspect, a wide mode signal is provided for switching the DRAM memory between a first data width configuration and a second data width configuration, the second data width configuration being twice as wide as the first data width configuration. In an alternate aspect of the present embodiment, the row address signal is inhibited from being column decoded with column address signals when the DRAM memory operates in the second data width configuration.
In a third aspect, the present invention provides a master row decoder circuit for enabling bitline access circuit blocks and row decoder blocks. The master row decoder circuit includes address input buffers, mode input buffers, column enabling logic, row enabling logic and a row predecoder. The address input buffers generate first complementary row address signals and second complementary row address signals in response to first and second address signals respectively. The mode input buffers generate a page mode signal and a differential access mode signal in response to first and a second mode signals respectively. The column enabling logic decodes the first complementary row address signals and the page mode signal for generating column control signals, the column control signals selectively enabling one half of the bitline access circuit blocks when the page mode signal is at a logic level corresponding to a short page access mode, and for enabling all of the bitline access circuit blocks when the page mode signal is at a logic level corresponding to a long page access mode. The row enabling logic decodes the second complementary row address signals and the differential access mode signal for generating row decoder control signals, the row decoder control signals activating one wordline driver in each row decoder block when the differential access mode signal is at a logic level corresponding to a single cell per bit mode, and two wordline drivers in each row decoder block when the differential access mode signal is at a logic level corresponding to a dual cell per bit mode. The row predecoder decodes the column control signals and the row decoder control signals for generating predecoded row address signals, the predecoded row address signals selectively enabling one half of the row decoder blocks when the page mode signal is at a logic level corresponding to the short page access mode, and all the row decoder blocks when the page mode signal is at a logic level corresponding to the long page access mode.
In a fourth aspect, the present invention provides a master row decoder circuit for enabling bitline access circuit blocks and row decoder blocks. The master row decoder includes an address input buffer, a mode input buffer, and column enabling logic. The address input buffer generates complementary row address signals in response to a row address. The mode input buffer generates a page mode signal in response to a mode signal, the mode signal dynamically switching the master row decoder operation between a short page access mode and a long page access mode. The column enabling logic decodes the complementary row address signals and the page mode signal for selectively enabling one half of the bitline access circuit blocks and one half of the row decoder blocks when the page mode signal is at a logic level corresponding to the short page access mode, and for enabling all of the bitline access circuit blocks and the row decoder blocks when the page mode signal is at a logic level corresponding to the long page access mode.
In an embodiment of the present aspect, each bitline access circuit block includes bitline sense amplifiers, bitline precharge circuits and column access devices.
In yet another embodiment of the present aspect, the column enabling logic includes a first logic gate having a first input for receiving one of the complementary row address signals and a second input for receiving the page mode signal, and a second logic gate having a first input for receiving the other of the complementary row address signals and a second input for receiving the page mode signal, where the first and second logic gates providing column control signals for enabling the bitline access circuit blocks.
In alternate aspects of the present embodiment, the first and second logic gates are NAND gates, and the row predecoder logic generates predecoded row address signals in response to column control signals, where the predecoded row address signals enable the row decoder block corresponding to the enabled bitline access circuit block.
In yet another aspect of the present embodiment, the row predecoder logic decodes the column control signals and row decoder control signals for selectively enabling sub-blocks of each row decoder block.
In an alternate embodiments of the present aspect, the bitline access circuits are coupled to a common databus, and each bitline access circuit block is coupled to a different databus.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.